AT91SAM7SE512-CU Atmel, AT91SAM7SE512-CU Datasheet - Page 102
AT91SAM7SE512-CU
Manufacturer Part Number
AT91SAM7SE512-CU
Description
IC ARM7 MCU FLASH 512K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE512-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
AT91SAM7SE512-CJ
AT91SAM7SE512-CJ
AT91SAM7SE512-CJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE512-CU
Manufacturer:
ALTERA
Quantity:
200
Part Number:
AT91SAM7SE512-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.2.2
102
SAM7SE512/256/32 Preliminary
Read Operations
Figure 19-1. Embedded Flash Memory Mapping
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added
in order to start access at following address during the second read, thus increasing perfor-
mance when the processor is running in Thumb mode (16-bit instruction set). See
Figure 19-3
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be pro-
grammed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
Flash Mode Register” on page
the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
and
Start Address
Figure
19-4.
Lock Region (n-1)
Flash Memory
Lock Region 0
Lock Region 1
111). Defining FWS to be 0 enables the single-cycle access of
32-bit wide
Lock Bit n-1
Lock Bit 0
Lock Bit 1
Page ( (n-1)*m )
Page (n*m-1)
Page (m-1)
Page 0
6222F–ATARM–14-Jan-11
Figure
19-2,
“MC
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