AT32UC3A0512-ALUR Atmel, AT32UC3A0512-ALUR Datasheet - Page 22
AT32UC3A0512-ALUR
Manufacturer Part Number
AT32UC3A0512-ALUR
Description
MCU 32BIT 512KB FLASH 144-LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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9.2.1
32058J–AVR32–04/11
Pipeline Overview
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the device-specific
“Peripherals” chapter of this data sheet.
Figure 9-1 on page 22
Figure 9-1.
AVR32 UC is a pipelined processor with three pipeline stages. There are three pipeline stages,
Instruction Fetch (IF), Instruction Decode (ID) and Instruction Execute (EX). The EX stage is
split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) sec-
tion and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 9-2 on page 23
Instruction memory controller
High Speed Bus master
Overview of the AVR32UC CPU
system
displays the contents of AVR32UC.
shows an overview of the AVR32 UC pipeline stages.
OCD
AVR32UC CPU pipeline
MPU
master
Speed
High
Bus
Data memory controller
Bus slave
Speed
High
CPU Local
Power/
control
Reset
master
Bus
AT32UC3A
22
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