ATMEGA88PA-PU Atmel, ATMEGA88PA-PU Datasheet - Page 277

MCU AVR 8K ISP FLASH MEM 28-DIP

ATMEGA88PA-PU

Manufacturer Part Number
ATMEGA88PA-PU
Description
MCU AVR 8K ISP FLASH MEM 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88PA-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88PA-PU
Manufacturer:
MICREL
Quantity:
2 001
Part Number:
ATMEGA88PA-PU
Manufacturer:
Atmel
Quantity:
27 830
25.3
25.3.1
8271C–AVR–08/10
Register Description
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during
EEPROM write or SPM.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATmega 48A/48PA.
• Bit 5 – Reserved
This bit is a reserved bit in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will
always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in ATmega 48A/48PA is a subset of the functionality in
ATmega88A/88PA/168A/168PA/328/328P. If the RWWSRE bit is written while filling the tempo-
rary page buffer, the temporary page buffer will be cleared and the data will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in ATmega 48A/48PA is a subset of the functionality in
ATmega88A/88PA/168A/168PA/328/328P. An LPM instruction within three cycles after BLBSET
and SELFPRGEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits
(depending on Z0 in the Z-pointer) into the destination register. See
Bits from Software” on page 272
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
0x37 (0x57)
Read/Write
Initial Value
SPMIE
R/W
7
0
RWWSB
R
6
0
for details.
R
5
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
PGWRT
R/W
2
0
”Reading the Fuse and Lock
PGERS
R/W
1
0
SELFPRGEN
R/W
0
0
SPMCSR
277

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