AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 14
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7.2
7.3
14
Debug and Test Features
Bus Matrix
AT91SAM9261 Preliminary
• Integrated Embedded In-circuit Emulator Real-Time
• Debug Unit
• Embedded Trace Macrocell: ETM9
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
• Five Masters and Five Slaves handled
• One Address Decoder Provided per Master
• Boot Mode Select Option
• Remap Command
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
– Medium+ Level Implementation
– Half-rate Clock Mode
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two 16-bit Counters
– One 3-stage Sequencer
– One 45-byte FIFO
– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the
– Round-Robin Arbitration (three modes supported: no default master, last accessed
– Burst Breaking with Slot Cycle Limit
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be Internal or External.
– Selection is made by BMS pin sampled at reset.
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD
Controller and USB Host Port.
default master, fixed default master)
internal boot, one for external boot, one after remap.
™
6062M–ATARM–23-Mar-09
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