AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 207
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 22-3. Read Burst, 32-bit SDRAM Access
22.5.3
6062M–ATARM–23-Mar-09
SDRAMC_A[12:0]
Border Management
D[31:0]
SDWE
SDCS
(Input)
SDCK
RAS
CAS
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
Row n
t
RCD
= 3
col a
Figure 22-4
CAS = 2
col b
Dna
below.
col c
AT91SAM9261 Preliminary
Dnb
col d
RP
) command and the active/read (t
Dnc
col e
Dnd
col f
Dne
Dnf
RCD
) com-
207
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