AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 241
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Part Number
Manufacturer
Quantity
Price
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25.3
25.4
6062M–ATARM–23-Mar-09
Processor Clock Controller
USB Clock Controller
Figure 25-1. Master Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
Note:
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see
When the PLL B output is stable, i.e., the LOCKB is set:
Figure 25-2. USB Clock Controller
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
MAINCK
PLLACK
PLLBCK
SLCK
The ARM Wait for Interrupt mode is entered with CP15 coprocessor operation. Refer to the Atmel
application note,
6217.
Source
Clock
USB
PMC_MCKR
CSS
Optimizing Power Consumption fo AT91SAM9261-based
USBDIV
Divider
/1,/2,/4
PMC_MCKR
Master Clock
Prescaler
PRES
AT91SAM9261 Preliminary
UDP
PMC_MCKR
Master
Divider
MDIV
Clock
Figure
UDP Clock (UDPCK)
25-2).
MCK
To the Processor
Clock Controller (PCK)
Systems, lit. number
241
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