ADUC836BS Analog Devices Inc, ADUC836BS Datasheet - Page 17

• Manufacturer Part Number: ADUC836BS
• Description: IC ADC DUAL 16BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP

ADC SFR INTERFACE
Both ADCs are controlled and configured via a number of SFRs that are summarized here and described in more detail in the
following sections.
ADCSTAT
ADCMODE ADC Mode Register. Controls general modes of
ADC0CON
ADC1CON
SF
ICON
ADCSTAT (ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions
such as reference detect and conversion overflow/underflow flags.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
REV. A
Name
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
–––
–––
ADC Status Register. Holds general status of the
primary and auxiliary ADCs.
operation for primary and auxiliary ADCs
Primary ADC Control Register. Controls specific
configuration of primary ADC.
Auxiliary ADC Control Register. Controls
specific configuration of auxiliary ADC.
Sinc Filter Register. Configures the decimation
factor for the Sinc
and auxiliary ADC update rates.
Current Source Control Register. Allows the user
to control of the various on-chip current source
options.
Description
Ready Bit for Primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conversion
or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers
until the RDY0 bit is cleared.
Ready Bit for Auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC.
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit (only active if primary or auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold.
When set, conversion results are clamped to all ones, if using external reference.
Cleared to indicate valid V
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all
zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not
to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC.
Reserved for Future Use
Reserved for Future Use
3
filter and thus the primary
D8H
00H
Yes
Table IV. ADCSTAT SFR Bit Designations
REF
.
–17–
ADC0M/H
ADC1L/H
OF0M/H
OF1L/H
GN0M/H
GN1L/H
Primary ADC 16-bit conversion result is held in
these two 8-bit registers.
Auxiliary ADC 16-bit conversion result is held in
these two 8-bit registers.
Primary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.
Auxiliary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.
Primary ADC 16-bit Gain Calibration Coefficient
is held in these two 8-bit registers.
Auxiliary ADC 16-bit Gain Calibration Coefficient
is held in these two 8-bit registers.
ADuC836