Z8F1601VN020EC00TR Zilog, Z8F1601VN020EC00TR Datasheet - Page 93
Z8F1601VN020EC00TR
Manufacturer Part Number
Z8F1601VN020EC00TR
Description
IC ENCORE MCU FLASH 16K 44PLCC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F1601VN020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F1601VN020EC00T
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Table 46. Watch-Dog Timer Control Register (WDTCTL)
Watch-Dog Timer Control Register Definitions
PS017610-0404
RESET
FIELD
ADDR
BITS
R/W
Watch-Dog Timer Control Register
POR
X
R
7
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 46, is a Read-Only
register that indicates the source of the most recent Reset event, indicates a Stop Mode
Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets
the upper four bits to 0.
Writing the
ister address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH,
and WDTL) to allow changes to the time-out period. These write operations to the
WDTCTL register address produce no effect on the bits in the WDTCTL register. The
locking mechanism prevents spurious writes to the Reload registers.
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-
out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both
set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1
and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This
bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP
mode. Reading this register also resets this bit.
WDT—Watch-Dog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A Stop
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
STOP
X
R
6
55H
,
AAH
WDT
unlock sequence to the Watch-Dog Timer Control (WDTCTL) reg-
X
R
5
EXT
R
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
FF0
R
3
0
R
2
0
Reserved
R
1
0
Watch-Dog Timer
Z8 Encore!
R
0
0
®
75
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