ZGP323LEP4008C Zilog, ZGP323LEP4008C Datasheet
ZGP323LEP4008C
Specifications of ZGP323LEP4008C
Related parts for ZGP323LEP4008C
ZGP323LEP4008C Summary of contents
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... Z8 GP Microcontrollers ZGP323L OTP MCU Family Product Specification PS023709-0208 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 GP, Z8 Encore!, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...
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... October 05 2005 PS023709-0208 Description Updated Ordering Information example section. Updated document with new Zilog logo and disclaimer section. Added Pin 22 to SMR block Input, Updated Ordering Information, added Caution for I/ O ports 0, 1 and 2 and added new Clock information. Updated Ordering Information ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Architectural Overview Zilog’s ZGP323L is an OTP-based member of the MCU family of infrared microcontrollers. With 237 B of general-purpose RAM and OTP, Zilog’s CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/ reception, and internal key-scan pull-up transistors. ...
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Development Features The features of ZGP323L include (see Table 2. Features Device ZGP323L OTP MCU Family • Low power consumption—11 mW (typical) • Temperature S = Standard 0 °C to +70 ° Extended -40 °C to ...
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Port 0: 0–3 pull-up transistors – Port 0: 4–7 pull-up transistors – Port 1: 0–3 pull-up transistors – Port 1: 4–7 pull-up transistors – Port 2: 0–7 pull-up transistors – EPROM Protection – WDT enabled at POR – Functional Block ...
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SCLK Clock Divider Edge Input Glitch Detect Filter Circuit PS023709-0208 HI16 LO16 8 8 16-Bit T16 TC16H TC16L HI8 LO8 8 8 8-Bit TC8H TC8L Figure 2. Counter/Timers Diagram Product ...
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... The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in described in Table in Figure 4 and described in 48-pin SSOP versions are displayed in For customer engineering code development erasable windowed cerdip packaging is offered in 20-pin, 28-pin, and 40-pin configurations. Zilog guarantee these packages for use in production. P25 P26 P27 P07 V XTAL2 ...
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... V 16–20 P20–P24 Note: *Windowed Cerdip. These units are intended to be used for engineering code development ® only. Zilog does not recommend/guarantee this package for production use. XTAL2 XTAL1 Figure 4. 28-Pin PDIP/SOIC/SSOP/CDIP* Pin Configuration Table 4. 28-Pin PDIP/SOIC/SSOP/CDIP* Pin Identification Pin Symbol 1– ...
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... XTAL2 XTAL1 Figure 5. 40-Pin PDIP/CDIP* Pin Configuration Note: *Windowed Cerdip. These units are intended to be used for engineering code development ® only. Zilog does not recommend/guarantee this package for production use. PS023709-0208 Direction Description Input Analog ref input; connect to V ...
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NC P25 P26 P27 P04 N/C P05 P06 P14 P15 P07 VDD VDD N/C P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 NC VSS Figure 6. 48-Pin SSOP Pin Configuration Table 5. 40- and 48-Pin Configuration 40-Pin PDIP/CDIP ...
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Table 5. 40- and 48-Pin Configuration (Continued) 40-Pin PDIP/CDIP PS023709-0208 ...
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Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) ...
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Port 0 (P07–P00) Port 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. ...
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Port 1 (P17–P10) Port 1 (see Figure Port 1 is configured as an input port. The output drivers are either push-pull or open-drain and are controlled by bit D1 in the PCON register. Note: The Port 1 direction is reset ...
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Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in DEMODULATION mode OTP Open-Drain I/O Out In Port ...
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Z8 GP OTP P31 (AN1) Pref1 P32 (AN2) P33 (REF2) From Stop Mode Recovery Source of SMR Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is ...
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T8 and T16 Common Functions—CTR1(0D)01H IRQ modes are described in Note: Comparators are powered down by entering STOP mode. For P31–P33 to be used in a Stop Mode Recovery source, these inputs must be placed into DIGITAL mode. 2 ...
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P34 T8_Out P31 P31 + - P30 (Pref1) P32 P32 + - P33 Figure 11. Port 3 Counter/Timer Output Configuration PS023709-0208 CTR0, D0 PCON MUX P3M D1 Comp1 CTR2, D0 Out 35 MUX T16_Out CTR1, D6 ...
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Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources ...
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Functional Description This device incorporates special functions to enhance the functionality of Z8 consumer and battery-operated applications. Program Memory This device addresses OTP memory. The first 12 bytes are reserved for interrupt vectors. These locations ...
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Location of first Byte of instruction executed after RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Figure 12. Program Memory Map (32 K OTP) Expanded Register File The register file has been expanded to allow for additional system control ...
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RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred expanded register group (see Figure 13). PS023709-0208 ZGP323L Product Specification 20 ...
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Register Pointer Working Register Group Pointer Register File (Bank 0)** Expanded Reg. Bank 0/Group ( (0) ...
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The upper nibble of the register pointer (see group bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Z8 GP ...
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LD LD for access to bank D register group 0) LD expanded register bank D and working group 7 of bank 0 for access CTRL2→register 71h LD ; CTRL2→register 71h Register File The register file (bank 0) consists ...
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Figure 15. Register Pointer—Detail Stack The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal ...
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Timers T8_Capture_HI—HI8(D)0BH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1. Field T8_Capture_HI T8_Capture_LO—L08(D)0AH This register holds the captured data from the ...
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Counter/Timer2 LS-Byte Hold Register—TC16L(D)06H Field T16_Data_LO Counter/Timer8 High Hold Register—TC8H(D)05H Field T8_Level_HI Counter/Timer8 Low Hold Register—TC8L(D)04H Field T8_Level_LO CTR0 Counter/Timer8 Control Register—CTR0(D)00H Table 7 lists and briefly describes the fields for this register. Table 7. CTR0(D)00H Counter/Timer8 Control Register Field ...
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Table 7. CTR0(D)00H Counter/Timer8 Control Register (Continued) Field Bit Position Counter_INT_Mask ------1- P34_Out -------0 *Indicates the value upon Power-On Reset. T8 Enable This field enables T8 when set (written Single/Modulo-N When set to 0 (Modulo-N), the counter reloads ...
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P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. T8 and T16 Common Functions—CTR1(0D)01H This register controls the functions in common with the T8 and T16. Table 8 lists and briefly describes ...
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Table 8. CTR1(0D)01H T8 and T16 Common Functions (Continued) Field Bit Position Initial_T8_Out/ ------1- Rising Edge Initial_T16_Out/ -------0 Falling_Edge *Default at Power-On Reset. **Default at Power-On Reset. Not reset with Stop Mode Recovery. Mode If the result is 0, the ...
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Transmit_Submode/Glitch Filter In TRANSMIT mode, this field defines whether T8 and T16 are in the PING-PONG mode or in independent normal operation mode. Setting this field to NORMAL OPERATION mode terminates the PING-PONG mode operation. When set to 10, T16 ...
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Table 9. CTR2(D)02H: Counter/Timer16 Control Register Field Bit Position T16_Enable 7------- Single/Modulo-N -6------ Time_Out --5----- T16 _Clock ---43--- Capture_INT_Mask -----2-- Counter_INT_Mask ------1- P35_Out -------0 *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with Stop ...
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For details, see the description of T16 DEMODULATION mode on page 40. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write this location. T16_Clock This bit defines ...
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Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the ...
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Reset T8_Enable Bit Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Figure 17. TRANSMIT Mode Flowchart PS023709-0208 T8 (8-Bit) TRANSMIT Mode No T8_Enable Bit Set CTR0, D7 Yes 0 CTR1, D1 Value Load TC8L Set T8_OUT Reset ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1 TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, D6), T8 counts down ...
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Using the same instructions for stopping the counter/timers and setting the status bits is Caution: not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because ...
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D1). T8 then continues counting from (see Figure 21 and Positive Figure 21. DEMODULATION Mode Count Capture Flowchart PS023709-0208 Figure 22). T8 (8-Bit) Count Capture T8 Enable (Set by User) No Yes Edge ...
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Disable TC8 Figure 22. DEMODULATION Mode Flowchart PS023709-0208 T8 (8-Bit) DEMODULATION Mode T8 Enable CTR0 Yes → TC8 FFH First Edge Present No Yes Enable TC8 T8_Enable Bit Set No Yes No Edge Present Yes T8 Timeout Set ...
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, D0 T16_OUT T16_OUT is 0. You can force ...
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Do not load these registers at the time the values are to be loaded into the counter/timer Caution: to ensure known operation. An initial count not allowed. An initial count of 0 causes T16 to count from ...
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CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this ...
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Initiating PING-PONG Mode First, ensure both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG mode (CTR1, D2; D3). These instructions can be in random order. Finally, ...
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During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Timer Output ...
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IRQ Register D6, D7 IRQ2 Interrupt Request Figure 28. Interrupt Block Diagram PS023709-0208 Stop Mode Recovery Source P33 0 P31 P32 Interrupt Edge Timer 16 Select IRQ0 IRQ1 IRQ3 IRQ IMR IPR Global Interrupt Enable Priority Logic Vector Select ZGP323L ...
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Table 11. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32 IRQ1 P33 IRQ2 P31, T IRQ3 T16 IRQ4 T8 IRQ5 LVD When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the ...
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... Most crystals have a frequency tolerance of less than 50 ppm (+/-0.005%). Crystal oscillators, however, require a much longer start-up time because the large loading capacitance slows down oscillation start-up. Zilog of no more than 10 pF for crystal oscillators. If the stray capacitance of the PCB or the crystal is High, the loading capacitance C1 and C2 should be further reduced to ensure stable oscillation before T page 83, for more information) ...
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STOP mode. The Stop Mode Recovery delay must be selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source. For resonator and crystal oscillation, the oscillation ground must ...
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Port Configuration Register The Port Configuration (PCON) register (see on Port located in the expanded register 2 at Bank F, location 00. PCON(FH)00H Default setting after reset. Figure 30. Port Configuration Register (PCON) ...
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Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 33 on page 52) is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and ...
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HALT mode (where TCLK sources interrupt logic). After Stop Mode Recovery, this bit is set OSC ÷ 2 ÷ 16 Stop Mode Recovery Source (D2, D3, and D4) These three bits of the SMR ...
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Table 13. SMR2(F)0DH:Stop Mode Recovery Register 2* (Continued) Field Bit Position Source ---432-- Reserved ------10 * Port pins configured as outputs are ignored as a SMR recovery source. † Indicates the value upon Power-On Reset. PS023709-0208 Value Description † W ...
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SMR VCC SMR P31 SMR P32 SMR P33 SMR P27 SMR P20 P23 SMR P20 P27 SMR D6 To ...
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Table 14. Stop Mode Recovery Source SMR:432 Note: Any Port 2 bit defined ...
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Stop Mode Recovery Register 2 (SMR2) This register determines the mode of Stop Mode Recovery for SMR2 SMR2(0F) Note: If used in conjunction with SMR, either of the two specified events causes a Stop ...
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Watchdog Timer Mode Register (WDTMR) The Watchdog Timer (WDT retriggerable one-shot timer that resets the Z8 reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, ...
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Table 15. Watchdog Timer Time Select WDTMR During Halt (D2) This bit determines whether or not the WDT is active during HALT mode indicates active during HALT. The ...
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WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP mode. Because the XTAL clock is stopped during STOP mode, the on-board RC has to be selected as the clock source to the WDT/POR ...
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Field Bit Position LVD 76543--- -----2-- ------1- -------0 *Default after POR. Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Voltage Detection and Flags ...
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CTR0(0D)00H Default setting after reset. **Default setting after reset. Not reset with Stop Mode Recovery. Figure 37. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) PS023709-0208 ZGP323L Product Specification 0 P34 ...
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CTR1(0D)01H PS023709-0208 ZGP323L Product Specification TRANSMIT Mode* R/W 0 T16_OUT is 0 initially* 1 T16_OUT is 1 initially DEMODULATION Mode Falling Edge Detection R 1 Falling Edge Detection W ...
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CTR1(0D)01H * Default setting after reset. **Default setting after reset. Not reset with Stop Mode Recovery. Figure 38. T8 and T16 Common Control Functions ((0D)01H: Read/Write) Notes: Ensure to differentiate between the TRANSMIT mode and DEMODULATION mode. Depending on which ...
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CTR2(0D)02H Default setting after reset. **Default setting after reset. Not reset with Stop Mode Recovery. Figure 39. T16 Control Register ((0D) 2H: Read/Write Except Where Noted) PS023709-0208 ZGP323L Product Specification 0 ...
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CTR3(0D)03H Default setting after reset. ** Default setting after reset. Not reset with Stop Mode Recovery. Figure 40. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted) Note: If Sync Mode is enabled, the first pulse of ...
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LVD(0D)0CH Default Figure 41. Voltage Detection Register Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. PS023709-0208 ...
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Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are displayed in Figure 55. PCON(0F)00H Default setting after reset. Figure 42. Port Configuration Register (PCON)(0F)00H: Write Only) PS023709-0208 ...
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SMR(0F)0BH Default setting after Reset Set after Stop Mode Recovery the XOR gate input Default setting after Reset. Must using a crystal or ...
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SMR2(0F)0DH Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery. * Default setting after reset the XOR gate input. Figure 44. Stop ...
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WDTMR(0F)0FH Default setting after reset. Figure 45. Watchdog Timer Register ((0F) 0FH: Write Only) Standard Control Registers R246 P2M(F6H Default setting after reset. Figure 46. Port 2 Mode Register (F6H: Write Only) ...
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R247 P3M(F7H Default setting after reset. Not reset with Stop Mode Recovery. Figure 47. Port 3 Mode Register (F7H: Write Only) PS023709-0208 ZGP323L Product Specification 0: Port 2 Open Drain * ...
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R248 P01M(F8H Default setting after reset; only P00, P01 and P07 are available in 20-pin configurations. Figure 48. Port 0 and 1 Mode Register (F8H: Write Only) PS023709-0208 ZGP323L Product Specification ...
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R249 IPR(F9H Figure 49. Interrupt Priority Register (F9H: Write Only) PS023709-0208 ZGP323L Product Specification Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C 011 A ...
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R250 IRQ(FAH Figure 50. Interrupt Request Register (FAH: Read/Write) R251 IMR(FBH Default setting after reset Only by using EI, DI instruction required before changing the IMR register. Figure 51. ...
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R252 Flags(FCH Figure 52. Flag Register (FCH: Read/Write) R253 RP(FDH Default setting after reset = 0000 0000. Figure 53. Register Pointer (FDH: Read/Write) PS023709-0208 ...
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R254 SPH(FEH Figure 54. Stack Pointer High (FEH: Read/Write) R255 SPL(FFH Figure 55. Stack Pointer Low (FFH: Read/Write) PS023709-0208 ZGP323L Product Specification General-Purpose Register ...
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Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure ...
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From Output Under Test Capacitance Table 18 lists the capacitances. Table 18. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Note ° Characteristics Table 19. ZGP323LS DC Characteristics Symbol Parameter V V Supply Voltage ...
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Table 19. ZGP323LS DC Characteristics (Continued) Symbol Parameter V V Output High Voltage 2.0–3.6 OH1 V Output High Voltage 2.0–3.6 OH2 (P36, P37, P00, P01) V Output Low Voltage 2.0–3.6 OL1 V Output Low Voltage 2.0–3.6 OL2 (P00, P01, P36, ...
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Table 19. ZGP323LS DC Characteristics (Continued) Symbol Parameter V Notes 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when V falls below strongly ...
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Table 20. ZGP323LE DC Characteristics (Continued) Symbol Parameter V I Supply Current 2.0 CC 3.6 I Standby Current 2.0 CC1 (HALT Mode) 3.6 I Standby Current 2.0 CC2 (STOP Mode) 3.6 2.0 3.6 I Standby Current LV (Low Voltage) V ...
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Table 21. ZGP323LA DC Characteristics (Continued) Symbol Parameter V V Output High Voltage 2.0–3.6 OH2 (P36, P37, P00, P01) V Output Low Voltage 2.0–3.6 OL1 V Output Low Voltage 2.0–3.6 OL2 (P00, P01, P36, P37) V Comparator Input 2.0–3.6 OFFSET ...
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Table 21. ZGP323LA DC Characteristics (Continued) Symbol Parameter V Notes 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when V falls below strongly ...
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AC Characteristics Figure 57 and Table 23 Clock IRQ N Clock Setup Stop Mode Recovery Source PS023709-0208 describe the Alternating Current (AC) characteristics Figure 57. AC Timing ...
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Table 23. AC Characteristics No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer ...
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Packaging Package information for all versions of ZGP323L are depicted in Figure 68. PS023709-0208 Figure 58. 20-Pin CDIP Package ZGP323L Product Specification 84 Figure 58 through Packaging ...
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Figure 59. 20-Pin PDIP Package Diagram Figure 60. 20-Pin SOIC Package Diagram PS023709-0208 ZGP323L Product Specification 85 Packaging ...
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Figure 61. 20-Pin SSOP Package Diagram PS023709-0208 ZGP323L Product Specification 86 Packaging ...
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PS023709-0208 Figure 62. 28-Pin CDIP Package ZGP323L Product Specification 87 Packaging ...
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Figure 63. 28-Pin SOIC Package Diagram PS023709-0208 ZGP323L Product Specification 88 Packaging ...
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Figure 64. 28-Pin PDIP Package Diagram PS023709-0208 ZGP323L Product Specification 89 Packaging ...
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DETAIL SEATING PLANE Figure 65. 28-Pin SSOP Package Diagram PS023709-0208 C MILLIMETER SYMBOL MIN NOM A 1.73 1.86 A1 0.05 0. 1.68 1.73 B 0.25 C 0.09 ...
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Figure 67. 40-Pin PDIP Package Diagram PS023709-0208 Figure 66. 40-Pin CDIP Package ZGP323L Product Specification 91 Packaging ...
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... Detail A Figure 68. 48-Pin SSOP Package Design Note: Check with Zilog assembly. PS023709-0208 Detail SEATING PLANE L 0-8˚ ® on the actual bonding diagram and coordinate for chip-on-board ZGP323L Product Specification CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH Packaging 92 ...
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Ordering Information 32 KB Standard Temperature: 0 °C to +70 °C Part Number Description ZGP323LSH4832G 48-pin SSOP 32K OTP ZGP323LSP4032G 40-pin PDIP 32K OTP ZGP323LSH2832G 28-pin SSOP 32K OTP ZGP323LSP2832G 28-pin PDIP 32K OTP ZGP323LSK2032E 20-pin CDIP 32K OTP 32 ...
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KB Standard Temperature: 0 °C to +70 °C Part Number Description ZGP323LSH4816G 48-pin SSOP 16K OTP ZGP323LSS2816G 28-pin SOIC 16K OTP ZGP323LSP4016G 40-pin PDIP 16K OTP ZGP323LSH2816G 28-pin SSOP 16K OTP ZGP323LSP2016G 20-pin PDIP 16K OTP ZGP323LSP2816G 28-pin PDIP ...
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KB Standard Temperature: 0 °C to +70 °C Part Number Description ZGP323LSH4808G 48-pin SSOP 8K OTP ZGP323LSP4008G 40-pin PDIP 8K OTP ZGP323LSH2808G 28-pin SSOP 8K OTP ZGP323LSP2808G 28-pin PDIP 8K OTP 8 KB Extended Temperature: –40 °C to +105 ...
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... ZGP323LAP4004G 40-pin PDIP 4K OTP ZGP323LAH2804G 28-pin SSOP 4K OTP ZGP323LAP2804G 28-pin PDIP 4K OTP Additional Components Part Number Description Visit the Zilog web site at components and development tools for the ZGP323L. For fast results, contact your local Zilog desired. PS023709-0208 Part Number ZGP323LSS2804G ZGP323LSH2004G ZGP323LSP2004G ZGP323LSS2004G ...
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... Pins Pins Package Type K = Windowed Cerdip P = PDIP H = SSOP S = SOIC Temperature Range ° °C (Standard -40 °C to +105 °C (Extended -40 °C to +125 °C (Automotive) Voltage Range 3.6 V Family Designation 323 = Family Designation P = OTP ZG=Zilog ZGP323L Product Specification 97 ® General-Purpose Family Ordering Information ...
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PS023709-0208 ZGP323L Product Specification 98 Ordering Information ...
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Index Numerics 16-bit counter/timer circuits 39 20-pin DIP package diagram 85 20-pin SSOP package diagram 86 28-pin DIP package diagram 89 28-pin SOICpackage diagram 88 28-pin SSOP package diagram 90 40-pin DIP package diagram 91 48-pin SSOP package diagram 92 ...
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T16 description functional 18 pin 5 E EPROM selectable options 57 expanded register file 19 expanded register file architecture 21 expanded register file control registers 64 flag 73 interrupt mask register 72 interrupt priority register ...
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O oscillator configuration 46 output circuit, counter/timer 42 P package information 20-pin DIP package diagram 85 20-pin SSOP package diagram 86 28-pin DIP package diagram 89 28-pin SOIC package diagram 88 28-pin SSOP package diagram 90 40-pin DIP package diagram ...
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Counter/Timer2 LS-Byte Hold 26 Counter/Timer2 MS-Byte Hold 25 Counter/Timer8 Control 26 Counter/Timer8 High Hold 26 Counter/Timer8 Low Hold 26 CTR2 Counter/Timer 16 Control 30 CTR3 T8/T16 Control 32 Stop Mode Recovery2 33 T16_Capture_LO 25 T8 and T16 Common ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS023709-0208 ZGP323L ...