ZGP323HEH4832C00TR Zilog, ZGP323HEH4832C00TR Datasheet - Page 16
ZGP323HEH4832C00TR
Manufacturer Part Number
ZGP323HEH4832C00TR
Description
IC Z8 GP MCU 32K OTP 48SSOP
Manufacturer
Zilog
Series
Z8® GP™r
Specifications of ZGP323HEH4832C00TR
Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
HLVD, POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
- Current page: 16 of 108
- Download datasheet (3Mb)
PS023807-0707
Notes:
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port. The output drivers are push-pull or
open-drain controlled by bit D2 in the PCON register.
If one or both nibbles are needed for I/O operation, they must be configured by writing to
the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port.
An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble
select.
put with outputting logic ONE, it is a floating port and will read back as ZERO.
The following instruction will set P00-P07 all LOW.
AND P0,#%F0
1. Internal pull-ups are disabled on any given pin or group of port
2. The Port 0 direction is reset to its default state following an SMR.
pins when programmed into output mode.
Product Specification
Pin Description
ZGP323H
11
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