Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 48
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Z32AN Series Data Sheet
7.2.3
7.2.4
7.2.5
DS0200-003
Single Write followed
Single Read followed
The SDRAM Controller leaves all pages open if possible. Banks are closed by page misses and refresh
commands.
Single Write (same
Byte, Half-Word or
Byte, Half-Word or
Single Read (same
Supported Configurations
SDRAM Performance
Open Bank Policy
immediately by
immediately by
Access Type
4-Burst Write
8-Burst Write
4-Burst Read
8-Burst Read
Single Write:
Single Read:
page)
page)
Word
Word
Column Addressing
Bank Addressing
Row Addressing
Configuration
Bank Available
Bank Available
Bank Available
Bank Available
Bank Available
Bank Available
Bank Available
Bank Available
Page Status
Page Miss
Page Miss
Page Miss
Page Miss
Page Miss
Page Miss
Page Miss
Page Miss
Page Hit
Page Hit
Page Hit
Page Hit
Page Hit
Page Hit
Page Hit
Page Hit
4K : A[11:0]
256 : A[7:0]
4 Meg x 16
4 : BA[1:0]
64 Mb
11-2-2-2-2-2-2-2
8-2-2-2-2-2-2-2
6-2-2-2-2-2-2-2
5-2-2-2-2-2-2-2
3-2-2-2-2-2-2-2
8-2-2-2-2-2-2-2
AHB Clocks
11-2-2-2
6-2-2-2
3-2-2-2
8-2-2-2
8-2-2-2
5-2-2-2
11-2
8-2
6-2
5-5
3-5
8-5
11
8
6
1
1
1
4K : A[11:0]
512 : A[8:0]
8 Meg x 16
4 : BA[1:0]
128 Mb
Notes
D-Cache or I-Cache line fill
D-Cache half-line dirty
D-Cache or I-Cache line fill
8K : A[12:0]
16 Meg x 16
512 : A[8:0]
4 : BA[1:0]
256 Mb
32 Meg x 16
8K : A[12:0]
4 : BA[1:0]
1K : A[9:0]
512 Mb
Page 35
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