Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 78
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
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Part Number
Manufacturer
Quantity
Price
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Z32AN Series Data Sheet
9.3.1
DS0200-003
Offset 000h: MCR_CTRL – MCR Control Register
31:24
27:24
18:16
14:13
12:10
08:07
05:03
02:00
Bits
23
22
21
20
19
15
09
06
Type
RW
RW
RW
RW
RW
RW
WO
RW
RW
RW
RW
RW
RW
RO
RO
RO
Reset
000
0h
00
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
FIFO Count (COUNT): Number of valid entries are contained in the MCR FIFO.
Card Time-out (CARD_TO_IEN): When set, enables card time-outs to cause an
interrupt.
Aux ADC (AUX_ADC_IEN): When set, enables interrupts when a new sample is
available in MCR_AUX_ADC.
FIFO Underflow (UFLO_IEN): When set, enables interrupts on a FIFO underflow.
FIFO Overflow (OFLO_IEN): When set, enables interrupts on a FIFO overflow.
FIFO Level (LVL_IEN): When set, enables interrupts on the number of FIFO entries
greater than or equal to the FIFO level.
Track “N” Timeout (TOn_IEN): When set, enables time-out interrupts from the
specified MCR track.
Bypass ADC (BYPASS): When set, enables digital inputs to bypassing the ADC.
Reserved
Track “N” Mode (MODEn): When set, the track is in ADC mode. When cleared, the
track is in peak-detection mode.
Soft Reset (SOFT): When written to ‘1’, resets the MCR state machines and FIFOs.
Does not affect analog or ADC registers. Writes of ‘0’ have no effect.
Threshold Mode (THRESH): Selects the threshold mode to use to all tracks:
DMA Enable (DMA): When set, enables DMA requests when FIFO level is reached or
exceeded.
FIFO Level (LVL): Sets the number of MCR FIFO entries required for a DMA request
or FIFO interrupt.
Track “N” Enable (IENn): Enables each track. When cleared, the track is disabled.
When set, the track is enabled.
0000: None, 0001: 1 entry, 0010: 2 entries, …, 1000: 8 entries
1001 - 1111: Invalid
00: Static thresholds
01: Enable 1/4 scaling thresholds
10: Enable 1/8 scaling thresholds
11: Enable 1/16 scaling thresholds
000: 1 FIFO entry, 001: 2 FIFIO entries, …, 111: 8 FIFO entries
Page 65
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