COP8SAA728M9 National Semiconductor, COP8SAA728M9 Datasheet - Page 40

IC MCU OTP 8BIT 1K 28SOIC

COP8SAA728M9

Manufacturer Part Number
COP8SAA728M9
Description
IC MCU OTP 8BIT 1K 28SOIC
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA728M9

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAA728M9
COP8SAA728M9B
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13.0 Instruction Set
13.1 INTRODUCTION
This section defines the instruction set of the COP8SAx
Family members. It contains information about the instruc-
tion set features, addressing modes and types.
13.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the follow-
ing features:
12.3 ADDRESSING MODES
The instruction set offers a variety of methods for speci-
fying memory addresses. Each method is called an ad-
dressing mode. These modes are classified into two cat-
egories:
transfer-of-control addressing modes. Operand address-
ing modes are the various methods of specifying an ad-
dress
Transfer-of-control addressing modes are used in con-
junction with jump instructions to control the execution
sequence of the software program.
13.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory
location is to be affected by that instruction. Several dif-
ferent operand addressing modes are available, allowing
memory locations to be specified in a variety of ways. An
instruction can specify an address directly by supplying
the specific address, or indirectly by specifying a register
pointer. The contents of the register (or in some cases,
two registers) point to the desired memory location. In the
immediate mode, the data byte to be used is contained in
the instruction itself.
Each addressing mode has its own advantages and dis-
advantages with respect to flexibility, execution speed,
and program compactness. Not all modes are available
with all instructions. The Load (LD) instruction offers the
largest number of addressing modes.
The available addressing modes are:
• Mostly single-byte opcode instructions minimize pro-
• One instruction cycle for the majority of single-byte
• Many single-byte, multiple function instructions such
• Three memory mapped pointers: two for register indi-
• Sixteen memory mapped registers that allow an opti-
• Ability to set, reset, and test any individual bit in data
• Register-Indirect LOAD and EXCHANGE instructions
• Unique instructions to optimize program size and
• Direct
gram size.
instructions to minimize program execution time.
as DRSZ.
rect addressing, and one for the software stack.
mized implementation of certain instructions.
memory
memory-mapped I/O ports and registers.
with optional automatic post-incrementing or decre-
menting of the register pointer. This allows for greater
efficiency (both in cycle time and program code) in
loading, walking across and processing fields in data
memory.
throughput efficiency. Some of these instructions are
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
for
operand
accessing
address
addressing
(reading
space,
or
including
modes
writing)
data.
and
the
40
• Register B or X Indirect
• Register B or X Indirect with Post-Incrementing/
• Immediate
• Immediate Short
• Indirect from Program Memory
The addressing modes are described below. Each de-
scription includes an example of an assembly language
instruction using the described addressing mode.
Direct. The memory address is specified directly as a byte
in the instruction. In assembly language, the direct ad-
dress is written as a numerical value (or a label that has
been defined elsewhere in the program as a numerical
value).
Example: Load Accumulator Memory Direct
Register B or X Indirect. The memory address is specified
by the contents of the B Register or X register (pointer
register). In assembly language, the notation [B] or [X] speci-
fies which register serves as the pointer.
Example: Exchange Memory with Accumulator, B Indirect
Register B or X Indirect with Post-Incrementing/
Decrementing. The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
of memory blocks with software loops. In assembly lan-
guage, the notation [B+], [B−], [X+], or [X−] specifies which
register serves as the pointer, and whether the pointer is to
be incremented or decremented.
Example: Exchange Memory with Accumulator, B Indirect
Intermediate. The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character ( # ) indicates an immediate operand.
Decrementing
LD A,05
X A,[B]
with Post-Increment
X A,[B+]
Memory Location
Memory Location
Memory Location
Accumulator
Accumulator
Accumulator
Reg/Data
0005 Hex
Reg/Data
0005 Hex
Reg/Data
0005 Hex
B Pointer
B Pointer
Memory
Memory
Memory
Contents
Contents
Contents
XX Hex
A6 Hex
01 Hex
87 Hex
05 Hex
03 Hex
62 Hex
05 Hex
Before
Before
Before
Contents
Contents
Contents
A6 Hex
A6 Hex
87 Hex
01 Hex
05 Hex
62 Hex
03 Hex
06 Hex
After
After
After

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