MC68HC705C8ACFN Freescale Semiconductor, MC68HC705C8ACFN Datasheet - Page 128

IC MCU 4MHZ 8K OTP 44-PLCC

MC68HC705C8ACFN

Manufacturer Part Number
MC68HC705C8ACFN
Description
IC MCU 4MHZ 8K OTP 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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Serial Communications Interface (SCI)
Technical Data
128
Freescale Semiconductor, Inc.
For More Information On This Product,
Character Length — The receiver can accommodate either 8-bit
or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When receiving 9-bit data,
bit R8 in SCCR1 is the ninth bit (bit 8).
Character Reception — During reception, the receive shift register
shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between the internal data bus and
the receive shift register.
After a complete character shifts into the receive shift register, the
data portion of the character is transferred to the SCDR, setting
the receive data register full (RDRF) flag. The RDRF flag can be
used to generate an interrupt.
Receiver Wakeup — So that the MCU can ignore transmissions
intended only for other receivers in multiple-receiver systems, the
MCU can be put into a standby state. Setting the receiver wakeup
enable (RWU) bit in SCI control register 2 (SCCR2) puts the MCU
into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the MCU out
of the standby state:
– Idle input line condition — If the PD0/RDI pin is at logic 1 long
– Address mark — If a logic 1 occurs in the most significant bit
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
Receiver Noise Immunity — The data recovery logic samples
each bit 16 times to identify and verify the start bit and to detect
noise. Any conflict between noise detection samples sets the
noise flag (NF) in the SCSR. The NF bit is set at the same time
that the RDRF bit is set.
Serial Communications Interface (SCI)
enough for 10 or 11 logic 1s to shift into the receive shift
register, receiver interrupts are again enabled.
position of a received character, receiver interrupts are again
enabled.
Go to: www.freescale.com
MC68HC705C8A — Rev. 3
MOTOROLA

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