MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 117

IC MCU 4MHZ 8K OTP 40-DIP

MC68HC705C8ACP

Manufacturer Part Number
MC68HC705C8ACP
Description
IC MCU 4MHZ 8K OTP 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACP

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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9.5.2 Mask Option Register 1
MC68HC705C8A — Rev. 3
MOTOROLA
Address:
SEC — Security Bit
IRQ — Interrupt Request Pin Sensitivity Bit
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
Mask option register 1 (MOR1) shown in
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin.
See
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
Erased:
Reset:
Read:
Write:
This bit is implemented as an EPROM cell and is not affected by
reset.
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
These EPROM bits enable the port B pullup devices.
Freescale Semiconductor, Inc.
4.3.3 Port B
For More Information On This Product,
1 = Security enabled
0 = Security off; bootloader able to be enabled
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
1 = Port B pullups enabled
0 = Port B pullups disabled
PBPU7
$1FF0
Bit 7
0
Figure 9-5. Mask Option Register 1 (MOR1)
EPROM/OTPROM (PROM)
Go to: www.freescale.com
PBPU6
Interrupts.
6
0
PBPU5
5
0
Unaffected by reset
PBPU4
4
0
PBPU3
Figure 9-5
3
0
EPROM/OTPROM (PROM)
PBPU2
2
0
is an EPROM
PBPU1
Control Registers
1
0
Technical Data
PBPU0/
COPC
Bit 0
0
117

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