MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 125

• Manufacturer Part Number: MC68HC705C8ACP
• Description: IC MCU 4MHZ 8K OTP 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACP

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

MC68HC705C8A — Rev. 3
MOTOROLA
$000D
$000E
$000F
$0010
$0011
Addr.
SCI Control Register 1
SCI Control Register 2
SCI Status Register
Baud Rate Register
SCI Data Register
Register Name
See page 136.
See page 130.
See page 131.
See page 133.
See page 129.
Figure 10-3. SCI Transmitter I/O Register Summary
(SCCR1)
(SCCR2)
(SCDR)
(SCSR)
(Baud)
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Reset:
Reset:
Reset:
Reset:
Reset:
For More Information On This Product,
Read:
Read:
Read:
Read: TDRE
Read:
Write:
Write:
Write:
Write:
Write:
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and
then writing data to the SCDR begins the transmission. At the start
of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of logic 1s. After the
preamble shifts out, the control logic transfers the SCDR data into
the shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the shift register, and a logic 1 stop
bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
Serial Communications Interface (SCI)
Bit 7
Bit 7
TIE
R8
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U
U
0
1
= Unimplemented
TCIE
Bit 6
TC
T8
U
U
6
0
1
SCP1
RDRF
Bit 5
RIE
5
0
0
0
U = Unaffected
SCP0
Unaffected by reset
IDLE
Bit 4
ILIE
M
U
4
0
0
0
Serial Communications Interface (SCI)
WAKE
Bit 3
OR
TE
U
U
3
0
0
SCR2
Bit 2
RE
NF
U
2
0
0
SCR1
RWU
Bit 1
Technical Data
SCI Operation
FE
U
1
0
0
SCR0
Bit 0
SBK
Bit 0
U
U
0
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