MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 150

IC MCU 4MHZ 8K OTP 40-DIP

MC68HC705C8ACP

Manufacturer Part Number
MC68HC705C8ACP
Description
IC MCU 4MHZ 8K OTP 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACP

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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Serial Peripheral Interface (SPI)
Technical Data
150
SPI — SPI Enable Bit
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR1 and SPR0 — SPI Clock Rate Bits
This read/write bit enables the SPI. Reset clears the SPE bit.
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
These read/write bits select the master mode serial clock rate, as
shown in
no effect on the serial clock. Reset has no effect on SPR1 and SPR0.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SPI enabled
0 = SPI disabled
1 = Master mode
0 = Slave mode
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
Serial Peripheral Interface (SPI)
Table
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Table 11-1. SPI Clock Rate Selection
SPR[1:0]
11-1. The SPR1 and SPR0 bits of a slave SPI have
00
01
10
11
Internal Clock
Internal Clock
Internal Clock
Internal Clock
SPI Clock Rate
MC68HC705C8A — Rev. 3
32
16
2
4
MOTOROLA

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