MC68HC705C9ACFN Freescale Semiconductor, MC68HC705C9ACFN Datasheet - Page 67

• Manufacturer Part Number: MC68HC705C9ACFN
• Description: IC MCU 2.1MHZ 16K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFN

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

RIE — Receiver Interrupt Enable Bit
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wakeup Enable Bit
SBK — Send Break Bit
9.13.4 SCI Status Register
The SCI status register (SCSR), shown in
Freescale Semiconductor
This read/write bit enables SCI interrupt requests when the RDRF flag or the OR flag becomes set.
Resets clear the RIE bit.
This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Resets clear the
ILIE bit.
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the PD1/TDO pin. Resets clear the TE bit.
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver
interrupts but does not affect the receiver interrupt flags. Resets clear the RE bit.
This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears
the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines
whether an idle input or an address mark brings the receiver out of standby state. Reset clears the
RWU bit.
Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of
logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears
the SBK bit.
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1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
1 = Transmission enabled
0 = Transmission disabled
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Break codes being transmitted
0 = No break codes being transmitted
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data SCDR complete
Receiver input idle
Noisy data
Framing error
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Figure
9-11, contains flags to signal the following conditions:
SCI I/O Registers
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