MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 37

IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part Number
MC68HC705J1ACDW
Description
IC MCU 4MHZ 1.2K OTP 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705J1ACDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
14
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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2.5 RAM
MC68HC705J1A — Rev. 4.0
Addr.
$0019
$001E
$001F
$07F0
$07F1
Mask Option Register
Register Name
NOTE:
Unimplemented
Unimplemented
COP Register
See page 99.
See page 41.
Reserved
(COPR)
(MOR)
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. Before processing an interrupt, the central processor
unit (CPU) uses five bytes of the stack to save the contents of the CPU
registers. During a subroutine call, the CPU uses two bytes of the stack
to store the return address. The stack pointer decrements when the CPU
stores a byte on the stack and increments when the CPU retrieves a byte
from the stack.
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Reset:
Reset:
Read:
Write:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
SOSCD
Bit 7
R
Go to: www.freescale.com
EPMSEC OSCRES
= Unimplemented
6
R
Memory
5
R
R = Reserved
Unaffected by reset
SWAIT
4
R
SWPDI
3
R
PIRQ
2
R
LEVEL
1
R
Technical Data
COPEN
Memory
COPC
Bit 0
R
0
RAM

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