MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 66

IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part Number
MC68HC705J1ACDW
Description
IC MCU 4MHZ 1.2K OTP 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705J1ACDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
14
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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Central Processor Unit (CPU)
SWI
TAX
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TXA
WAIT
3.8 Opcode Map
Technical Data
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Source
Form
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
Software Interrupt
Transfer Accumulator to Index Register
Test Memory Byte for Negative or Zero
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
Table 3-6. Instruction Set Summary (Sheet 6 of 6)
Operation
See
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
3-7.
Central Processor Unit (CPU)
Go to: www.freescale.com
PCH
PCL
PC
SP
SP
SP
SP
SP
Interrupt Vector High Byte
Interrupt Vector Low Byte
Description
(SP) – 1; Push (PCH)
(SP) – 1; Push (CCR)
(PC) + 1; Push (PCL)
(SP) – 1; Push (X)
(SP) – 1; Push (A)
(M) – $00
(SP) – 1; I
A
X
(A)
(X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
( )
–( )
?
:

1
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
H I N Z C
— 1 — — —
— — — — —
— —
— — — — —
on CCR

Effect
MC68HC705J1A — Rev. 4.0
— — —
 
INH
INH
DIR
INH
INH
INH
INH
IX1
IX
3D
4D
5D
6D
7D
9F
8F
83
97
dd
ff
10
2
4
3
3
5
4
2
2

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