MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 98

• Manufacturer Part Number: MC68HC705J1ACDW
• Description: IC MCU 4MHZ 1.2K OTP 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705J1ACDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 14
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Computer Operating Properly (COP) Module
7.3 Operation
7.3.1 COP Watchdog Timeout
7.3.2 COP Watchdog Timeout Period
7.3.3 Clearing the COP Watchdog
Technical Data
NOTE:
NOTE:
Operation of the COP is described in this subsection.
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/V
voltage is between V
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. See timer status and control register
in
The minimum COP timeout period is seven times the RTI period. The
COP is cleared asynchronously with the value in the RTI divider; hence,
the COP timeout period will vary between 7x and 8x the RTI period.
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see
Section 9. Multifunction Timer
Freescale Semiconductor, Inc.
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SS
and V
DD
. Periodically clearing the counter starts
Module.
MC68HC705J1A — Rev. 4.0
Figure
7-1).
PP
pin