MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 27

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

2.8 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that controls the following options:
Take the following steps to program the mask option register (MOR):
SOSCD — Short Oscillator Delay Bit
EPMSEC — EPROM Security Bit
OSCRES — Oscillator Internal Resistor Bit
Freescale Semiconductor
1. Apply the programming voltage, V
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, t
4. Clear the MPGM bit.
5. Reset the MCU.
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The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following
reset or exit from stop mode is 4064 t
The EPMSEC bit controls access to the EPROM/OTPROM.
The OSCRES bit enables a 2-MΩ internal resistor in the oscillator circuit.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
COP watchdog (enable or disable)
External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive)
Port A external interrupts (enable or disable)
Port pulldown resistors (enable or disable)
STOP instruction (stop mode or halt mode)
Crystal oscillator internal resistor (enable or disable)
EPROM security (enable or disable)
Short oscillator delay (enable or disable)
Address:
Program the OSCRES bit to logic 0 in devices using low-speed crystal or
RC oscillators with external resistor.
Reset:
Read:
Write:
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
SOSCD
$07F1
Bit 7
Figure 2-4. Mask Option Register (MOR)
EPMSEC
6
OSCRES
cyc
PP
5
. Setting SOSCD enables a 128 t
, to the IRQ/V
MPGM
NOTE
SWAIT
Unaffected by reset
.
4
PP
SWPDI
pin.
3
PIRQ
2
cyc
LEVEL
1
stabilization delay.
Mask Option Register
COPEN
Bit 0
27