MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 28

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MC68HC705KJ1CDW

Manufacturer Part Number
MC68HC705KJ1CDW
Description
IC MCU 4MHZ 1.2K OTP 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705KJ1CDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
10
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705KJ1CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Memory
SWAIT — Stop-to-Wait Conversion Bit
SWPDI — Software Pulldown Inhibit Bit
PIRQ — Port A External Interrupt Bit
LEVEL —External Interrupt Sensitivity Bit
COPEN — COP Enable Bit
2.9 EPROM Programming Characteristics
28
Programming Voltage
Programming Current
Programming Time
1. V
IRQ/V
IRQ/V
Per Array Byte
MOR
The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction
as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t
The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the
pulldown inhibit bits in the port pulldown inhibit registers.
The PIRQ bit enables the PA0–PA3 pins to function as external interrupt pins.
The LEVEL bit controls external interrupt triggering sensitivity.
The COPEN bit enables the COP watchdog.
DD
1 = Halt mode enabled
0 = Halt mode not enabled
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
1 = COP watchdog enabled
0 = COP watchdog disabled
= 5.0 Vdc ± 10%, V
PP
PP
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Characteristic
SS
Table 2-1. EPROM Programming Characteristics
= 0 Vdc, T
A
= –40
°
C to +85
°
C
cyc
occurs after exiting halt mode.
Symbol
t
t
MPGM
EPGM
V
I
PP
PP
16.0
Min
—¦
4
4
(1)
16.5
Typ
3.0
Freescale Semiconductor
Max
17.0
10.0
Unit
mA
ms
V

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