MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 30

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Computer Operating Properly Module (COP)
3.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register
at location $07F0 (see
the IRQ/V
If the main program executes within the COP timeout period, the clearing routine should be executed only
once. If the main program takes longer than the COP timeout period, the clearing routine must be
executed more than once.
3.4 Interrupts
The COP watchdog does not generate interrupts.
3.5 COP Register
The COP register (COPR) is a write-only register that returns the contents of EPROM location $07F0
when read.
COPC — COP Clear Bit
3.6 Low-Power Modes
The STOP and WAIT instructions have the following effects on the COP watchdog.
3.6.1 Stop Mode
The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog.
30
This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results.
PP
pin voltage.
Address:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option register
to logic 1.
Reset:
Read:
Write:
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Figure
$07F0
Bit 7
U
3-1). Clearing the COP bit disables the COP watchdog timer regardless of
= Unimplemented
U
6
Figure 3-1. COP Register (COPR)
U
5
U = Unaffected
NOTE
NOTE
U
4
U
3
U
2
U
1
Freescale Semiconductor
COPC
Bit 0
0