MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 33

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five
CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the
instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU
operations.
4.2 Features
Features of the CPU include:
The programming model is shown in
4.3 CPU Control Unit
The CPU control unit fetches and decodes instructions during program operation. The control unit selects
the memory locations to read and write and coordinates the timing of all CPU operations.
4.4 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from
the instruction set by the CPU control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register (CCR).
Freescale Semiconductor
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4.0-MHz bus frequency on standard part
8-bit accumulator
8-bit index register
11-bit program counter
6-bit stack pointer
Condition code register with five status flags
62 instructions
8 addressing modes
Power-saving stop, wait, halt, and data-retention modes
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Figure
4-1.
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