MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 59

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

6.3.3.1 STOP
The STOP instruction:
After exit from stop mode by external interrupt, the COP watchdog counter immediately begins counting
from $0000 and continues counting throughout the oscillator stabilization delay.
After exit from stop mode by reset:
6.3.3.2 WAIT
The WAIT instruction has no effect on the COP watchdog.
6.3.4 Timer
Effects of STOP and WAIT on the timer are discussed here.
6.3.4.1 STOP
The STOP instruction:
After exiting stop mode by external interrupt, the timer immediately resumes counting from the last value
before the STOP instruction and continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation
from its reset state.
6.3.4.2 WAIT
The WAIT instruction has no effect on the timer.
6.3.5 EPROM/OTPROM
Effects of STOP and WAIT on the EPROM/OTPROM are discussed here.
Freescale Semiconductor
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Clears the COP watchdog counter
Disables the COP watchdog clock
The COP watchdog counter immediately begins counting from $0000.
The COP watchdog counter is cleared at the end of the oscillator stabilization delay and begins
counting from $0000 again.
Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and control register, disabling timer
interrupt requests and removing any pending timer interrupt requests
Disables the clock to the timer
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option register
to logic 1.
Immediately after exiting stop mode by external interrupt, service the COP
to ensure a full COP timeout period.
To prevent a COP timeout during wait mode, exit wait mode periodically to
service the COP.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
NOTE
NOTE
NOTE
Effects of Stop and Wait Modes
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