MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 60

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MC68HC705KJ1CDW

Manufacturer Part Number
MC68HC705KJ1CDW
Description
IC MCU 4MHZ 1.2K OTP 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705KJ1CDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
10
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705KJ1CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Low-Power Modes
6.3.5.1 STOP
The STOP instruction during EPROM programming clears the EPGM bit in the EPROM programming
register, removing the programming voltage from the EPROM.
6.3.5.2 WAIT
The WAIT instruction has no effect on EPROM/OTPROM operation.
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU register contents at V
as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during
which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
To take the MCU out of data-retention mode:
6.5 Timing
60
1. Drive the RESET pin to logic 0.
2. Lower the V
1. Return V
2. Return the RESET pin to logic 1.
INTERNAL
INTERNAL
ADDRESS
(NOTE 2)
(NOTE 1)
(NOTE 3)
IRQ/V
Notes:
IRQ/V
DD
CLOCK
RESET
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
OSC
BUS
PP
DD
to normal operating voltage.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
PP
voltage. The RESET pin must remain low continuously during data-retention mode.
t
t
ILIH
RL
Figure 6-1. Stop Mode Recovery Timing
OSCILLATOR STABILIZATION DELAY
(NOTE 4)
$07FE
$07FE
$07FE
(5)
$07FE
RESET OR INTERRUPT
$07FE
VECTOR FETCH
$07FF
Freescale Semiconductor
DD
voltages as low

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