MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 67

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output.
DDRB[3:2] — Data Direction Register B Bits
Figure 7-8
Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0
disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port B data direction. Reset clears DDRB[3:2], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
shows the I/O logic of port B.
Note:
Address:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Reset:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These
Read:
Write:
bits are available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
READ DDRB
WRITE DDRB
WRITE PORTB
READ PORTB
WRITE PDRB
$0005
Bit 7
0
0
Figure 7-7. Data Direction Register B (DDRB)
= Unimplemented
RESET
6
0
0
Figure 7-8. Port B I/O Circuitry
5
0
See Notes
DDRBx
PDRBx
PBx
Table 7-2
NOTE
4
0
summarizes the operation of the port B pins.
DDRB3
3
0
SWPDI
DDRB2
2
0
100-µA
PULLDOWN
1
0
See Note
PBx
Bit 0
0
Port B
67