MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 72

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Resets and Interrupts
8.2.1 Power-On Reset
A positive transition on the V
A 4064-t
stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until
all reset sources are inactive.
8.2.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t
logic level at the RESET pin.
72
RESET Pulse Width
cyc
(internal clock cycle) delay after the oscillator becomes active allows the clock generator to
Notes:
ADDRESS BUS
Notes:
ADDRESS BUS
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
1. Internal clock, internal address bus, and internal data bus are not available externally.
The power-on reset is strictly for power-up conditions and cannot be used
to detect drops in power supply voltage.
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
3. Internal clock, internal address bus, and internal data bus are not available externally.
INTERNAL
INTERNAL
INTERNAL
DATA BUS
INTERNAL
INTERNAL
INTERNAL
OSC1 PIN
DATA BUS
CLOCK
RESET
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
CLOCK
V
DD
(NOTE 1)
Characteristic
DD
pin generates a power-on reset.
Figure 8-2. Power-On Reset Timing
Figure 8-3. External Reset Timing
Table 8-1. External Reset Timing
$07FE
t
RL
$07FE
OSCILLATOR STABILIZATION DELAY
$07FE
cyc
$07FE
generates an external reset. A Schmitt trigger senses the
NOTE
$07FE
$07FE
$07FE
NEW
PCH
$07FE
$07FF
(2)
Symbol
NEW
PCL
$07FE
t
RL
NEW PC
DUMMY
$07FE
NEW PCH NEW PCL
Min
1.5
NEW PC
CODE
OP
$07FF
Freescale Semiconductor
Max
—
Unit
t
cyc