MC68HC705KJ1CP Freescale Semiconductor, MC68HC705KJ1CP Datasheet - Page 35
MC68HC705KJ1CP
Manufacturer Part Number
MC68HC705KJ1CP
Description
IC MCU 4MHZ 1.2K OTP 16-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MCHRC705KJ1CDWE.pdf
(108 pages)
Specifications of MC68HC705KJ1CP
Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
10
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705KJ1CP
Manufacturer:
FREESCALE
Quantity:
20 000
4.5 CPU Registers
The M68HC05 CPU contains five registers that control and monitor MCU operation:
CPU registers are not memory mapped.
4.5.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
results of ALU operations.
4.5.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional
address of the operand. The index register also can serve as a temporary storage location or a counter.
4.5.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address
in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked.
Freescale Semiconductor
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•
•
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Accumulator
Index register
Stack pointer
Program counter
Condition code register
Reset:
Reset:
Read:
Read:
Write:
Write:
Reset:
Read:
Write:
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Bit
15
0
0
Bit 7
Bit 7
= Unimplemented
14
0
0
13
0
0
6
6
12
0
0
Figure 4-4. Stack Pointer (SP)
Figure 4-3. Index Register (X)
Figure 4-2. Accumulator (A)
11
0
0
5
5
10
0
0
Unaffected by reset
Unaffected by reset
9
0
0
4
4
8
0
0
7
1
1
3
3
6
1
1
5
1
2
2
4
1
3
1
1
1
2
1
1
1
Bit 0
Bit 0
Bit
0
1
CPU Registers
35