MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 104

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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8
8.3
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
8.4
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
8.5
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in
sampling, the analog value is stored on the capacitor and held until the end of conversion. During
this hold time, the analog input is disconnected from the internal A/D system and the external
voltage source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Freescale
8-6
A/D converter during STOP mode
A/D converter during WAIT mode
Port D analog input
Note:
Analog
input
pin
Figure 8-2 Electrical model of an A/D input pin
The analog switch is closed during the 12 cycle sample time only.
Figure
ANALOG TO DIGITAL CONVERTER
Input protection device
8-2. Sampling time is limited to 12 bus clock cycles. After
< 2pF
+ ∼20V
- ∼0.7V
junction
leakage
1 µA
≥ 50kΩ
capacitance
≥ 10pF
DAC
V
RL
MC68HC05B6
Rev. 4.1

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