MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 106

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
9.1.1
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (t
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time t
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external
RC circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be
great enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a t
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see
A software distinction between a power-on reset and an external reset can be made using the
POR bit in the miscellaneous register (see
9.1.2
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
Note:
Freescale
9-2
1 (set)
0 (clear) –
Miscellaneous
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
Power-on reset
Miscellaneous register
A power-on reset has occurred.
No power-on reset has occurred.
Section
Address
$000C POR
RESETS AND INTERRUPTS
3.8.
bit 7
(1)
Section
INTP
bit 6
INTN
bit 5
9.1.2).
INTE
bit 4
PORL
SFA
bit 3
delay start-up sequence. t
bit 2
SFB
PORL
bit 1
SM WDOG
PORL
Section
) from when the
MC68HC05B6
bit 0
has elapsed.
(2)
1.2).
?001 000?
Rev. 4.1
on reset
PORL
State
is

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