MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 204

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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14
E.4.3
For erased EPROM verification, PD4 must be at ‘0’. In this case, erased EPROM verification
executes as described in
If PD4 is at ‘1’, the program initially checks the state of the security bit. If the security bit is active
(‘0’), the program will not enter serial bootstrap and the red LED will flash. Otherwise the serial
bootstrap program will be executed according to
The serial routine communicates through the SCI with an external host, typically a PC, by means
of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Refer to
diagram of a suitable circuit.
Note:
The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed
of programming the 15 kbytes, four bytes are programmed while the data is simultaneously
transmitted back and forward in full duplex. This implies that while 4 bytes are being programmed
the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the
serial loader is as follows:
The protocol is as follows:
Freescale
E-16
1) EPROM locations
2) EEPROM1 locations
1) The MC68HC705B16 sends the last two bytes programmed to the host as a
2) In response to the first byte prompt, the host sends the first address byte.
3) After receiving the first address byte, the MC68HC705B16 sends the next
Data format is not ASCII, but 8-bit binary, so a complementary program must be run by
the host to supply the required format. Such a program is available for the IBM PC from
Freescale.
prompt; this also allows the host to verify that programming has been carried
out correctly.
byte programmed.
[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]
Address n must have the two least significant bits at zero so that n, n+1, n+2 and n+3
have identical most significant bits. These blocks of four bytes do not need to be
contiguous, as a new address is transmitted for each new group.
[address n high] [address n low] [data(n)] [dummy data 1] [dummy data 2] [dummy data 3]
The same four byte protocol of data exchange is used, but only the first data value is
programmed at address n. The three following dummy data values must be sent to be
in agreement with the protocol, but are not significant.
EEPROM/EPROM/RAM serial bootstrap
Section E.4.1
before control is given to the serial routine.
MC68HC705B16
Figure E-3
and
Figure
Figure E-8
E-4.
for a schematic
MC68HC05B6
Rev. 4.1

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