MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 292

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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E1PGM – EEPROM charge pump enable/disable
E6LAT – EPROM programming latch enable bit
E6PGM – EPROM program enable bit
ECLK – External clock output bit
EE1P – EEPROM protect bit
EE1P – EEPROM protection bit
EEPROM
EEPROM control register
EEPROM options register
EEPROM/ECLK control
ELAT – EPROM programming latch enable bit
EPGM – EPROM programming bit
EPP – EPROM protect
EPPT – EPROM protect test bit
EPROM
EPROM control register
EPROM electrical characteristics
EPROM registers
EPROM/EEPROM/ECLK control register
external clock
external interrupt
F
FE – Framing error flag
H
high speed operation
Freescale
vi
erase operation
programming operation
read operation
STOP mode
WAIT mode
E1ERA
E1LAT
E1PGM
ECLK
EE1P
SEC
ECLK
control register
options register
program operation
programming operation
read operation
ELAT
EPGM
EPPT
E1ERA
E1LAT
E1PGM
E6LAT
E6PGM
13–2
E–9, F–9
3–1
C–6
E–9
3–3
4–3
C–6
C–6
3–4
E–7
E–6
E–7
H–9
3–3
E–7
3–4
E–7
E–6
,
,
2–12
,
C–5
3–3
,
,
,
,
F–9
3–7
,
,
3–7
9–7
F–7
F–6
C–6
F–7
F–7
F–7
F–6
,
3–5
E–5
,
C–6
C–7
3–5
D–4
I–1
E–5
,
C–7
E–5
,
6–17
H–10
,
,
F–5
,
E–6
E–5
,
F–5
3–6
C–5
E–9
F–6
,
,
,
H–8
C–6
F–6
H–12
4–3
,
F–5
,
E–28
C–6
F–9
H–8
,
E–6
,
G–2
F–26
,
F–6
,
E–6
C–6
H–29
,
3–4
H–9
,
F–6
,
INDEX
,
I
I/O pin states
I/O port structure
ICF1 – Input capture flag 1
ICF2 – Input capture flag 2
IDLE – Idle line detect flag
IEDG1 – Input edge 1
ILIE – Idle line interrupt enable
Input capture registers
input/output programming
INTE – External interrupt enable
interrupts
INTP, INTN – External interrupt sensitivity options
IRQ
IRQ sensitivity
L
LBCL – Last bit clock
low power modes
M
M – Mode
Mask option register
mask options
maskable hardware interrupts
maskset errata
MC68HC05B16
MC68HC05B32
MC68HC05B4
MC68HC05B6
ICR1
ICR2
priorities
SCI
SWI
SLOW
STOP
WAIT
PBPD
PCPD
RTIM
RWAT
WWAT
MC68HC05B6
block diagram
memory map
block diagram
memory map
block diagram
memory map
block diagram
mask options
memory map
pinouts
9–7
9–10
9–6
5–7
5–8
6–11
E–8
2–8
E–8
2–6
E–8
2–9
E–8
E–8
12–1
9–6
4–2
,
9–9
,
,
D–1
,
,
D–1
G–1
F–8
F–9
F–8
4–2
,
F–8
F–8
D–5
G–3
A–3
3–2
1–3
D–3
G–2
A–2
1–3
12–2
1–3
,
,
,
,
,
,
H–1
6–13
,
5–5
H–11
H–11
4–2
H–11
H–11
H–11
,
4–1
12–3
6–16
5–6
5–7
9–7
6–14
3–9
,
9–9
MC68HC05B6
3–9
,
9–9

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