MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 293

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MC68HC05B8
MC68HC705B16
MC68HC705B16N
MC68HC705B32
MC68HC705B5
mechanical dimensions
memory map
Miscellaneous register
modes of operation
N
NF – Noise error flag
nonmaskable software interrupt
O
OCF1 – Output compare flag 2
OCF2 – Output compare flag 2
OCIE – Output compares interrupt enable
OLV1 – Output level 1
OLV2 – Output level 2
Options register
options register
MC68HC05B6
block diagram
memory map
block diagram
memory map
block diagram
memory map
block diagram
memory map
block diagram
memory map
MC68HC05B16
MC68HC05B32
MC68HC05B4
MC68HC05B6
MC68HC05B8
MC68HC705B16
MC68HC705B16N
MC68HC705B32
MC68HC705B5
INTE
INTP, INTN
POR
SFA
SFB
SM
WDOG
jump to any address
low power modes
single chip mode
SEC
EE1P
EPP
PBPD
2–9
3–10
3–10
H–12
C–7
3–9
3–9
H–12
C–8
,
3–10
,
,
3–10
,
,
B–1
9–2
9–9
C–1
7–3
7–3
3–9
,
E–1
H–3
B–3
E–3
F–3
H–5
C–3
B–2
E–2
F–2
H–4
C–2
F–1
,
9–4
A–3
3–2
B–3
,
D–5
G–3
C–3
7–3
6–17
2–1
E–3
H–5
9–9
2–6
5–5
5–5
F–3
12–4
2–4
,
12–5
5–6
5–7
9–6
,
12–6
5–4
INDEX
OPTR – options register
OR – Overrun error flag
oscillator connections
Output compare registers
P
parallel bootstrap
PBPD – Port B pull-down
PBPD – Port B pull-down resistors
PCPD – Port C pull-down
PCPD – Port C pull-down resistors
pin configurations
pins
PLCC
PLM
POR – Power-on reset bit
port registers
PORTD – Port D data register
ports
power-on reset
programmable timer
Pulse
pulse length modulation
PCPD
RTIM
RWAT
WWAT
EE1P – EEPROM protection bit
SEC – Security bit
OCR1
OCR2
IRQ
OSC1, OSC2
PA0–PA7, PB0–PB7, PC0–PC7
PD0/AN0–PD7/AN7
PLMA, PLMB
RDI, TDO
RESET
SCLK
TCAP1
TCAP2
TCMP1, TCMP2
VDD, VSS
VPP1
VRH, VRL
block diagram
clock selection
PLMA, PLMB
PORTA, PORTB
PORTC
PORTD
A and B
C
D
block diagram
registers
5–11
5–11
12–1
4–3
4–3
PLMA, PLMB
2–10
C–7
2–13
2–13
C–8
5–9
5–10
C–7
C–7
2–10
2–11
2–10
4–4
4–5
4–2
2–13
2–13
9–2
2–10
,
E–13
12–1
2–11
2–13
7–2
7–1
5–2
9–3
7–4
2–11
4–4
2–12
,
5–11
3–7
6–17
5–11
3–6
E–19
2–13
E–8
E–8
3–9
,
,
D–4
,
,
,
,
C–7
8–3
F–8
F–9
9–2
F–13
C–8
C–8
3–7
2–13
,
H–16
Freescale
vii

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