MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 37

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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2.4.3
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see
internal operations and thus reduces power consumption. The SLOW mode function should not
be enabled while using the A/D converter or while erasing/programming the EEPROM unless the
internal A/D RC oscillator is turned on.
2.4.3.1
SM — Slow mode
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
MC68HC05B6
Rev. 4.1
1 (set)
0 (clear) –
Miscellaneous
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
(bit 1, $000C)
SM–bit
SLOW mode
OSC1
Miscellaneous register
pin
The system runs at a bus speed 16 times lower than normal
(f
SCI, A/D and timer.
The system runs at normal bus speed (f
MODES OF OPERATION AND PIN DESCRIPTIONS
Oscillator
OSC
Figure 2-4 Slow mode divider block diagram
/32). SLOW mode affects all sections of the device, including
Section
Address
$000C
OSC2
pin
3.8.
POR
bit 7
Control logic
f
OSC
Figure
INTP
bit 6
2-4). This feature permits a slow down of all the
INTN
bit 5
÷
2
INTE
bit 4
OSC
f
OSC
SFA
bit 3
/2
/2).
bit 2
SFB
÷
16
bit 1
SM
Main internal clock
f
OSC
WDOG ?001 000?
/32
bit 0
Freescale
on reset
State
2-9
2

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