MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 64

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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5
5.2.2
The timer status register ($13) is a read only register and contains the status bits corresponding
to the four timer interrupt conditions – ICF1,OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF1 — Input capture flag 1
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
the TSR and then the input capture low register 1 ($15).
OCF1 — Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then reading or writing the output compare 1 low register ($17).
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19).
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
Freescale
5-6
Timer status (TSR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 The timer status register is read or written when TOF is set, and
1) The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Timer status register (TSR)
A valid input capture has occurred.
No input capture has occurred.
A valid output compare has occurred.
No output compare has occurred.
Timer overflow has occurred.
No timer overflow has occurred.
Address
$0013
PROGRAMMABLE TIMER
ICF1
bit 7
OCF1
bit 6
TOF
bit 5
ICF2
bit 4
OCF2
bit 3
bit 2
bit 1
MC68HC05B6
bit 0
Undefined
Rev. 4.1
on reset
State

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