MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 69

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.3
A software force compare is required in many applications. To achieve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOLV2 for OCR2) in the timer control register are used. These bits always read as ‘zero’,
but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the respective
output level (TCMP1 and TCMP2 pins).
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide range of applications including fixed
frequency generation.
Note:
5.5
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM
conversions, with a choice of two repetition rates (see
5.5.1
MC68HC05B6
Rev. 4.1
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
A software force compare will affect the corresponding output pin TCMP1 and/or
TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
Software force compare
Pulse Length Modulation (PLM)
Pulse length modulation registers A and B (PLMA/PLMB)
Address
Address
$000A
$000B
PROGRAMMABLE TIMER
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
Section
bit 4
bit 4
7).
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
bit 0
bit 0
Freescale
0000 0000
0000 0000
on reset
on reset
State
State
5-11
5

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