MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 76

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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6
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate
and for SCT0–SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Freescale
6-4
Note:
Transmitter clock
SCT0 – SCT2
rate control
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling).
This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can
be obtained.
transmitter
(
÷
÷
NT)
16
SERIAL COMMUNICATIONS INTERFACE
Figure 6-2 SCI rate generator division
SCP1
7
SPC0
6
SCT2
5
SCP0 – SCP1
Baud rate register
rate control
prescaler
SCT1
(
÷
4
NP)
Internal processor clock
SCT0
3
SCR2
2
SCR1
1
SCR0
0
$000D
Figure
SCR0 – SCR2
rate control
receiver
(
÷
NR)
6-2). This register
Receiver clock
MC68HC05B6
Rev. 4.1

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