MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 82

no-image

MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC705B16CFN
Manufacturer:
MOT
Quantity:
2 132
Part Number:
MC68HC705B16CFN
Manufacturer:
1
Quantity:
1 000
Part Number:
MC68HC705B16CFNE
Manufacturer:
FREESCALE
Quantity:
2 512
6
6.11
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
6.11.1
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written.
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in
6.11.2
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
Freescale
6-10
SCI control 1 (SCCR1)
SCI data (SCDR)
Figure
Figure
Figure 6-1
SCI registers
Serial communications data register (SCDR)
Serial communications control register 1 (SCCR1)
6-1. All data is received with the least significant bit first.
6-1. All data is received with the least significant bit first.
shows this register as two separate registers, RDR and TDR. The RDR
SERIAL COMMUNICATIONS INTERFACE
Address
Address
$000E
$0011
bit 7
bit 7
R8
bit 6
bit 6
T8
bit 5
bit 5
bit 4
bit 4
M
WAKE CPOL CPHA LBCL Undefined
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
MC68HC05B6
bit 0
bit 0
0000 0000
Rev. 4.1
on reset
on reset
State
State

Related parts for MC68HC705B16CFN