MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 87

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed and the line will go
idle.
RE — Receiver enable
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited.
RWU — Receiver wake-up
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1). When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1)
zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually
send whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code,
the transmitter sends at least one high bit to guarantee recognition of a valid start bit.
MC68HC05B6
Rev. 4.1
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Transmitter enabled.
Transmitter disabled.
Receiver enabled.
Receiver disabled.
SERIAL COMMUNICATIONS INTERFACE
Freescale
6-15
6

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