MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 82
MC68HC908GP32CP
Manufacturer Part Number
MC68HC908GP32CP
Description
IC MCU 8MHZ 32K FLASH 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908GP32CFB.pdf
(410 pages)
Specifications of MC68HC908GP32CP
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908GP32CP
Manufacturer:
ROCKWELL
Quantity:
201
Part Number:
MC68HC908GP32CP
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Resets and Interrupts
4.4.2.1 SWI Instruction
4.4.2.2 Break Interrupt
4.4.2.3 IRQ Pin
4.4.2.4 CGM
4.4.2.5 TIM1
Technical Data
80
NOTE:
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
A logic 0 on the IRQ pin latches an external interrupt request.
The CGM can generate a CPU interrupt request every time the phase-
locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
TIM1 CPU interrupt sources:
•
•
TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter reaches the modulo value programmed in the TIM1
counter modulo registers. The TIM1 overflow interrupt enable bit,
TOIE, enables TIM1 overflow CPU interrupt requests. TOF and
TOIE are in the TIM1 status and control register.
TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x.
The channel x interrupt enable bit, CHxIE, enables channel x
TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1
channel x status and control register.
Resets and Interrupts
MC68HC908GP32
•
MC68HC08GP32
MOTOROLA
—
Rev. 6
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