MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 148

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

M•CORE M210 Central Processor Unit (CPU)
Technical Data
148
The supervisor programming model consists of the user model plus 16
additional 32-bit general-purpose registers (R[15:0]’, or the alternate
file), the entire PSR, and a set of status/control registers (CR[12:0]).
Setting the S bit in the PSR enables supervisor mode operation.
The alternate file allows very low overhead context switching for
real-time event handling. While the alternate file is enabled,
general-purpose operands are accessed from it.
The vector base register (VBR) determines the base address of the
exception vector table. Exception shadow registers EPC and EPSR are
used to save the states of the program counter and PSR, respectively,
when an exception occurs. Shadow registers FPC and FPSR save the
states of the program counter and PSR, respectively, when an exception
occurs.
Scratch registers (SS[4:0]) are used to handle exception events.
The global control (GCR) and status (GSR) registers can be used for a
variety of system monitoring tasks.
The supervisor programming model includes the PSR, which contains
operation control and status information. In addition, a set of exception
shadow registers is provided to save the state of the PSR and the
program counter at the time an exception occurs. A separate set of
shadow registers is provided for fast interrupt support to minimize
context saving overhead.
Five scratch registers are provided for supervisor software use in
handling exception events. A single register is provided to alter the base
address of the exception vector table. Two registers are provided for
global control and status.
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA