MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 180
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Non-Volatile Memory FLASH (CMFR)
9.2 Introduction
Technical Data
180
9.8.5
9.8.5.1
9.8.5.2
9.8.5.3
9.8.6
9.8.7
9.9
9.10
This section describes the operation of the embedded FLASH memory.
The FLASH memory can be read, programmed, and erased from a
single external programming voltage supply, V
erase operations are enabled through the use of an internal charge
pump.
The CDR MoneT FLASH uses the Motorola one-transistor bitcell
(MoneT). The 128-Kbyte CMFR array is divided into 16-Kbyte
(16,384 bytes) array blocks. The CMFR array size is created by using
eight array blocks.
The primary function of the CMFR is to serve as electrically
programmable and erasable NVM to store program instructions and/or
data. It is a class of nonvolatile solid state silicon memory device
consisting of an array of isolated elements, a means for selectively
adding and removing charge to the elements electrically and a means of
selectively sensing the stored charge in the elements. When power is
removed from the device, the stored charge of the isolated elements are
retained.
The CMFR is arranged into two major sections as shown in
The first section is the MoneT array used to store system program and
data. The second section is the bus interface unit (BIU) that controls
access and operation of the CMFR array.
Freescale Semiconductor, Inc.
For More Information On This Product,
Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Non-Volatile Memory FLASH (CMFR)
Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Erase Pulse Amplitude and Width Modulation . . . . . . . . . . 219
Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Erase Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Erasing Shadow Information Words. . . . . . . . . . . . . . . . 219
Go to: www.freescale.com
PP
. The program and
MMC2107 – Rev. 2.0
Figure
MOTOROLA
9-1.
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