MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 184

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Non-Volatile Memory FLASH (CMFR)
Technical Data
184
To improve system performance, the BIU accesses information in the
array at 32 bytes per access. These 32 bytes are copied in a read page
buffer aligned to the low-order addresses. A CMFR array contains two
non-overlapping read page buffers. The first read page buffer is
associated to the lower array blocks. The second read page buffer is
associated to the higher array blocks. Read access time of the data in
the current read page buffers is one system clock, while the time to read
a new page into a page buffer and access the required information is two
system clocks. These accesses are known as an on-page read and an
off-page read, respectively. To prevent the BIU from accessing an
unnecessary page from the array, the CMFR monitors the address to
determine if the required information is in one of the two current read
page buffers and the access is valid for the module. This strategy allows
the CMFR to have a two-clock read for an off-page access and one-clock
for an on-page access. In normal operation write accesses to the CMFR
array are not allowed, a write access causes a bus error.
The CMFR requires an external program or erase voltage, V
program or erase the array. Special control logic is included to require a
specific series of read and write accesses.
To improve program performance, the CMFR programs up to eight
unique 64-byte pages simultaneously in eight separate array blocks.
These 64 bytes are aligned to the low-order addresses to form a
program page buffer.
Each of the pages being programmed simultaneously are located at the
same block offset address. Erasing is performed on one or more of the
selected array blocks simultaneously.
An extra row (256 bytes) of the CMFR array is used to provide reset
configuration information and is called shadow information. This row
may be accessed by setting the SIE bit in the CMFR module
configuration register and accessing the CMFR array. The shadow
information is in the lowest array block 0 of the CMFR array. Note that
the shadow row is erased with block 0.
Freescale Semiconductor, Inc.
For More Information On This Product,
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
PP
MOTOROLA
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