MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 190

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Non-Volatile Memory FLASH (CMFR)
Technical Data
190
NOTE:
NOTE:
When SIE = 1, only the program page buffer associated with the lowest
block can be programmed. The other program page buffers cannot be
accessed and do not apply any programming voltages to their array
blocks while programming the shadow information. The shadow
information is in block 0.
LOCKCTL — Lock Control Bit
If LOCKCTL is set before PROTECT[7:0] is cleared, the device must use
debug mode to program or erase the CMFR.
DIS — Disable Bit
The address range of the shadow information is the entire address
range of the array, but the high order array addresses, are not used
to encode the location.
The read-always, set-once LOCKCTL bit controls the write-lock
function. Once the LOCKCTL bit is set in normal operation, the
write-lock can only be disabled again by a master reset. The
LOCKCTL bit is writable if the device is in debug mode.
Setting the LOCKCTL bit locks the SUPV[7:0], DATA[7:0] and
PROTECT[7:0] bits. Writing to these bits has no effect; the cycle ends
normally and the bits do not change.
The default reset state of LOCKCTL is 0. It can be set once after
master reset to allow protection of the write-locked register bits after
initialization.
If the LOCKCTL bit and write-locked register bits are written
simultaneously, the new value does not affect the current cycle.
The read-always DIS bit disables array information. Writing to DIS has
no effect if the SES bit is set. When DIS is set, the array is disabled
and the CMFR BIU does not respond to array accesses.
The reset value is defined during reset configuration by the external
D28 pin.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Write-locked registers protected
0 = Write-lock disabled
1 = Array information disabled
0 = Array information enabled
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
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