MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 203

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

9.7.2 Array Addressing
9.7.2.1 Read Page Buffers
MMC2107 – Rev. 2.0
MOTOROLA
Information in the array is accessed in 32-byte pages. Two read page
buffers are aligned to the low order addresses. The first page buffer is
for the lower array blocks. The second page buffer is for the higher array
blocks. Access time of information in the read page buffers is one system
clock. Access time for an off-page read is two system clocks. To prevent
the BIU from accessing an unnecessary page from the array, the CMFR
monitors the address to determine if the required information is within
one of the two read page buffers and the access is valid for the module.
This strategy allows the CMFR to have a 2-clock read for an off-page
access and a 1-clock read for an on-page access.
Writing to the array while not in a program/erase sequence causes a bus
error.
The two 32-byte read page buffers are fully independent and are located
in two separate read sections of the array. The BIU monitors the status
and address of each page buffer. The status of the read page buffers are
usually valid, but are made invalid by these operations:
Once EHV is set, SES cannot be changed; attempts to read or write
the array or CMFRRC cause bus errors.
The default reset state of EHV disables program or erase pulses
(EHV = 0). A master reset while EHV = 1 terminates the high-voltage
operation and the CMFR generates the required sequence to disable
the high voltage without damage to the high-voltage circuits.
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Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Program/erase pulse enabled
0 = Program/erase pulse disabled
Reset
Programming write
Erase interlock write
Setting the EHV bit
Clearing the SES bit
Setting or clearing the SIE bit
Exiting stop mode
Exiting disable mode
Exiting boot mode
Non-Volatile Memory FLASH (CMFR)
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Non-Volatile Memory FLASH (CMFR)
Registers and Memory Map
Technical Data
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