MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 229

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
NOTE:
NOTE:
RFD[2:0] — Reduced Frequency Divider Field
In external clock mode, the RFD[2:0] bits have no effect.
See
LOCEN — Loss of Clock Enable Bit
In external clock mode, the LOCEN bit has no effect.
DISCLK — Disable CLKOUT Bit
FWKUP — Fast Wakeup Bit
When FWKUP = 0, if the PLL or OSC is enabled and unintentionally lost
in stop mode, the PLL wakes up in self-clocked mode or reference clock
mode depending on the clock that was lost.
In external clock mode, the FWKUP bit has no effect on the wakeup
sequence.
The binary value written to RFD[2:0] is the PLL frequency divisor. See
Table
relock delay. Changes in clock frequency are synchronized to the
next falling edge of the current system clock. To avoid surpassing the
allowable system operating frequency, write to RFD[2:0] only when
the LOCK bit is set.
The LOCEN bit enables the loss of clock function. LOCEN does not
affect the loss of lock function.
The DISCLK bit determines whether CLKOUT is driven. Setting the
DISCLK bit holds CLKOUT low.
The FWKUP bit determines when the system clocks are enabled
during wakeup from stop mode.
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
1 = Loss of clock function enabled
0 = Loss of clock function disabled
1 = CLKOUT disabled
0 = CLKOUT enabled
1 = System clocks enabled on wakeup regardless of PLL lock
0 = System clocks enabled only when PLL is locked or operating
10-3. Changing RFD[2:0] does not affect the PLL or cause a
status
normally
10-6.
Go to: www.freescale.com
Clock Module
Memory Map and Registers
Technical Data
Clock Module
229

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