MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 327

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

15.10.2 Pulse Accumulator Overflow (PAOVF)
15.10.3 Pulse Accumulator Input (PAIF)
15.10.4 Timer Overflow (TOF)
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
NOTE:
NOTE:
PAOVF is set when the 16-bit pulse accumulator rolls over from $FFFF
to $0000. If the PAOVI bit in TIMPACTL is also set, PAOVF generates
an interrupt request. Clear PAOVF by writing a 1 to it.
When the fast flag clear all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in TIMPAFLG.
PAIF is set when the selected edge is detected at the PAI pin. In event
counter mode, the event edge sets PAIF. In gated time accumulation
mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the
PAI bit in TIMPACTL is also set, PAIF generates an interrupt request.
Clear PAIF by writing a 1 to it.
When the fast flag clear all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in TIMPAFLG.
TOF is set when the timer counter rolls over from $FFFF to $0000. If the
TOI bit in TIMSCR2 is also set, TOF generates an interrupt request.
Clear TOF by writing a 1 to it.
When the timer channel 3 registers contain $FFFF and TCRE is set,
TOF never gets set even though the timer counter registers go from
$FFFF to $0000.
When the fast flag clear all bit, TFFCA, is set, any access to the timer
counter registers clears timer flag register 2. The TFFCA bit is in timer
system control register 1 (TIMSCR1).
When TOF is set, it does not inhibit future overflow events.
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Modules (TIM1 and TIM2)
Go to: www.freescale.com
Timer Modules (TIM1 and TIM2)
Technical Data
Interrupts
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