MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 35

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
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Freescale Semiconductor, Inc.
For More Information On This Product,
Gated Mode, Continuous Scan Timing . . . . . . . . . . . . . . . 491
Star-Ground at the Point of Power Supply Origin. . . . . . . . 493
Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . . 494
Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . 494
External Multiplexing of Analog Signal Sources. . . . . . . . .496
Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . 497
Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Master Mode — 1-Clock Read and Write Cycle. . . . . . . . .515
Master Mode — 2-Clock Read and Write Cycle. . . . . . . . .515
Internal (Show) Cycle Followed . . . . . . . . . . . . . . . . . . . . . . . .
Internal (Show) Cycle Followed
Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 523
Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
Top-Level Tap Module and Low-Level (OnCE)
Top-Level TAP Controller State Machine . . . . . . . . . . . . . .540
IDCODE Register Bit Specification . . . . . . . . . . . . . . . . . .545
OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Low-Level (OnCE) Tap Module Data Registers (DRs). . . . 554
OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . . 559
OnCE Command Register (OCMR) . . . . . . . . . . . . . . . . . . 562
OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . . 564
OnCE Status Register (OSR) . . . . . . . . . . . . . . . . . . . . . . .568
OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . 570
OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . . 576
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by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
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